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  https://wodewangzhishime.blogspot.com/2024/02/blog-post.html . Ref:  https://wodewangzhishime.blogspot.com/2024/02/blog-post.html  . . . .  John : See the 1st picture.  It's an extreme condition.  RJ45 is indeed at down cycle.  Therefore,  the clock line of R0 is at down cycle.  However,  the parallel output line of R0 is at up cycle.  Me: RJ45's Circuit is hacked by hacker.  Me: R0 can't output its value onto the parallel output line.  John : Correct. See the 2nd picture.  It's another extreme example. Rj45 provide power supply to the modulator.  In fact,  the modulator is at the Up Cycle.  The clock line of R0 is at the Up Cycle too.  However,  the parallel input line of R0 is at the down system.  . Me: R0 can't be input.  . John : It's true. 

  https://wodewangzhishime.blogspot.com/2023/12/blog-post_14.html   . Ref:  https://wodewangzhishime.blogspot.com/2023/12/blog-post_14.html . . . Me: There're 4 pictures above. . We mention the 1st picture. There is a full wave rectifier. . .When the smoothing capacitor discharge, the gap between the Up and Down cycle is filled. . Consequently, the wave-form of the direct current become smooth. . John: OK. . Me: Now, we look at the 2nd picture. . Case 1. high frequency  <--- The curve is very smooth. . The discharge of the smoothing capacitor can easily fill the gap. . Case 2. middle frequency <--- The curve isn't smooth. . The discharge of the smoothing capacitor can hardly fill the gap. . Case 3. low frequency <--- The curve can't continue. . . The direct current is broken. . The discharge of the smoothing capacitor can't fill the gap. . John: Now, we look at the 2nd picture. . . 1) In direct current, if the frequency is high, the discharge of the smoothi...

  https://wodewangzhishime.blogspot.com/2023/12/blog-post_43.html . Ref:  https://wodewangzhishime.blogspot.com/2023/12/blog-post_43.html  . . . . John: There're 2 pictures above.  The 1st one is the original one.  R0 send out a signal of (0111). Me: Ok. John : Now, we see the 2nd picture.  . Me: Ok.  . John: Because the parallel output line of R0 is a branch of RJ45's Clock line, hacker hack the RJ45's Clock line and change the signal to (1000). .

https://wodewangzhishime.blogspot.com/2023/12/blog-post_13.html . Ref:  https://wodewangzhishime.blogspot.com/2023/12/blog-post_13.html  . . . John : See the Picture above.  There's a frequency mixer which mix the signal from the output of R0 and the signal from the Clock line of RJ45.  Me: R0 output.  Therefore,  RJ45 Clock line must be in down cycle.  . 1) The Signal from the Clock line of RJ45 must be wave inside which there is no carrier wave.  . 2) The carrier wave should be the output from R0. . 3) And then,  the signal from both R0 and RJ45 mix together at the frequency mixer.

  https://wodewangzhishime.blogspot.com/2023/12/blog-post_12.html . Ref:  https://wodewangzhishime.blogspot.com/2023/12/blog-post_12.html . . . . . Me: The upper picture use the inverters to delay the circuit. . However, the lower picture use the JK-Flip Flop to delay the circuit.

https://wodewangzhishime.blogspot.com/2023/12/sequential-99.html . . Ref:  https://wodewangzhishime.blogspot.com/2023/12/sequential-99.html . . .  . . . . Me: This article ( https://wodewangzhishime.blogspot.com/2023/12/blog-post_11.html ) mention that if I input 3-2-1-4, it stack overflow. Becuase 3-2 are too close to each other. .  . John: It is the problem of frequency. Me: Yes, . . Look at the 1st picture of this article. . It is an RJ45 circuit. .  This circuit use a capacitor and an inductor to form a filter. John: What's the filter for?? Me: For filtering signal. . . It let the signal within the boundary of frequency pass through. John: That mean, it let 3-2 enter the ground. Me: Yes,

https://wodewangzhishime.blogspot.com/2023/12/blog-post_11.html . . Ref:  https://wodewangzhishime.blogspot.com/2023/12/blog-post_11.html   . . . . Me: The following 4 articles mention how data-field work in RAM.  . 1)  https://wodewangzhishime.blogspot.com/2021/11/httpswodewangzhishime_96.html 2)  https://kamchihau.blogspot.com/2022/10/httpskamchihau_17.html?m=1 3)  https://wodewangzhishime.blogspot.com/2022/06/satellite-for-loop.html 4)  https://kamchihau.blogspot.com/2022/11/httpskamchihau.html . Me: Ok. . John:  There're 3 fields of data inside a "register of the RAM". They are, . Subject [],  object [],  Value [].   . I use (((Mov object, value))) as an example.  <--- In C++, it is ((( int object = value ))); . Originally, it is (((Mov register_a, value)))  <--- Note: in C++, it is (((int register_a = value;))) Me: If the field of value can be left shift, the contents of the field of object will be affected and ...

https://wodewangzhishime.blogspot.com/2023/12/sequential-94-cross.html . Ref:  https://wodewangzhishime.blogspot.com/2021/09/httpswodewangzhishime_42.html?m=1 . . . Me: https://wodewangzhishime.blogspot.com/2023/12/sequential-94-cross.html  . .This article mention that if you put too many inverters, the circuit delay too much. . Consequently, stack overflow occur. . Today, we give one more example in which the cirucit doesn't put too many inverters, however, stack overflow sitll occur. . I'm gonna input 3-2-1-4.   3-2 comply with the combination of NPN-PNP. . Look at the above picture. . There're 2 inverters only. . However, 3-2 both comply with the combination of NPN-PNP. . Consequently, stack overflow occur. . John: Because, 3-2 are closed to each other. . The frequency is too high. Me: In this case, stack overflow occur. . .

  https://wodewangzhishime.blogspot.com/2023/12/blog-post_2.html . Ref:  https://wodewangzhishime.blogspot.com/2023/12/blog-post_2.html  .  . . Me: You may consult it . . https://wodewangzhishime.blogspot.com/2023/12/blog-post_2.html .  Inverter is to delay the current flow.  Normally, we put a pair of inverter. . In a single Up cylce, I input 3-2-1-4, indeed, only "3" can be accepted. Why ?? Because, only "3" comply with the combination of NPN-PNP. . If you put too many inverters, the consequency is that not only "3" comply with the combination of NPN-PNP, but, "2" also comply with the combination of NPN-PNP. . Consequently, stack overflow occur.

https://wodewangzhishime.blogspot.com/2023/12/blog-post.html?m=1 . Ref:  https://wodewangzhishime.blogspot.com/2022/03/httpswodewangzhishime_53.html?m=1 . . . . . 1) About stack overflow, 2) Look at the 1st and 2nd pictures. . Note: The inverter delay the fow of current. The speed of the flow of current of line one is slower than the speed of the flow of current of line two. . 3) When the combination is npn-pnp, the up cycle is at the falling edge.  . 4) Look at the 3rd picture.  . John: When you input 3-2-1-4 to the gate of R1 during one up cycle, indeed, only 3 has the combination of NPN and PNP. .   And then , 2-1-4 are discarded. 3. npn pnp 2.  npn npn (discarded) 1.  npn npn (discarded) 4.  pnp npn (discarded) . John: Look at the last picture. . It is a RJ45 circuit. . .During an Up cycle, there're 3-2-1-4. . Me: Indeed, Port A only input with 3. . .And then, 2-1-4 are discarded. . Why ?? . John: Because, only "3" comply with the combination ...

  https://wodewangzhishime.blogspot.com/2023/12/sequential-90-enabling-line.html . Ref:  https://wodewangzhishime.blogspot.com/2023/12/sequential-90-enabling-line.html . . . John: The 1st picture is a circuit of flip flop. I guess you know that . . When set and reset is 1-0 -> 1 0-1 -> 0 0-0 -> remain the same.  1-1 -> toggle or illegal.  . John: Do you see an Up cycle on the clock line? Me: Yes,. John: This Up cycle is stable.  Now, see  the 2nd picture. There is an Up cycle on the clock line. This up cycle cover B1 and B2.  However, . B1-> stable. B2-> Unstable. .

  https://wodewangzhishime.blogspot.com/2023/11/httpswodewangzhishime_29.html . Ref: https://wodewangzhishime.blogspot.com/2023/11/httpswodewangzhishime_29.html . . . . . John : This article is about the "width" of data bus, e.g., 4 bits, 8 bits, 32 bits.  https://wodewangzhishime.blogspot.com/2022/04/httpswodewangzhishime_23.html?m=1 . You might have a look first.  Me: Ok. . John : See the above 2nd Picture. All control bus, data bus and address bus are the branch of Clock line of RJ45. . Me: In another words,  if hacker hack the Clock line of RJ45,  hacker can hack the system bus (Control, address and data bus). . John : Yes, take a look.  . 1) Address bus. . 2) Data bus, e.g., parallel input output line, serial input line.  . __ . 3) Control bus,  e.g.,  interrupt status [ RJ45 clock line], Falling edge trigger[ true ],   Left_Right_Shift status [ Right shift ], Load_Shift_status [  shifting ] .   Acknowledge [Slave] B...

https://wodewangzhishime.blogspot.com/2023/11/ref-httpswodewangzhishime.html?m=1 . Ref: https://wodewangzhishime.blogspot.com/2021/08/httpswodewangzhishime_26.html?m=1  . . . Me: See the Picture above.  It's a RJ45 circuit. Because there's current flow in the Server's side, there's current flow in the Client's side. . John : It's wrong.  There's power source in the client side. It's 2 V.  Even if there's no current flow in the Server side,  there's current flow in the Client Side. . Me: I assume that.  There's a "packaged wave". Inside it, there's a single carrier wave. . John: Ok. . Me: They are from the Server side. . John : Ok. . Me : The "packaged wave" and the "carrier wave" will enter the physical layer. . John: Ok. . Me: The packaged wave will become the clock line of the physical layer while the carrier wave will become the "data input" in the physical layer.  . John: Yes,. .

https://wodewangzhishime.blogspot.com/2023/08/blog-post.html?m=1 . Ref: https://wodewangzhishime.blogspot.com/2021/09/httpswodewangzhishime_11.html . . . . . . John: Look at the first picture. Ther're 2 way of connection of RJ45. Both ways are OK. Let me explain the 2nd picture. Me: OK. John: When Port A is being input, Port B is with the status of outputing. Me: OK. . John: Look at the 3rd picture. When Port B is being input, Port A is with the status of outputing.

  https://wodewangzhishime.blogspot.com/2023/07/me-look-at-this-article.html?m=1 . Ref:  https://kamchihau.blogspot.com/2023/08/blog-post.html   . . John: If the direction of current flow of port B is "occassionally" same as that of port A, there will be carrier wave formed. . Me: OK. John: Look at the picture above. Those carrier wave will affect the data input of Port A. Me: Those carrier wave also affect the Clock line. Consequently, register R1, 2, 3 become unstable.

  https://wodewangzhishime.blogspot.com/2023/07/blog-post.html . Ref: https://wodewangzhishime.blogspot.com/2023/07/blog-post.html . . . . . John: The 1st picture is an operational amplifier.  4.5 V- 0.5 v = 4 V. Me: Ok. John : Now, see the 2nd picture.   (-0.5v) - (-4.5v) = 4 V. . Me: Yes, it's 4 V as well.  But, the direction of current flow is different. . . John: See the 2nd picture.  (Rd+) Should connect to 3. However,  if I let (RD +) connect to 6, the difference between them is the same. 

  https://wodewangzhishime.blogspot.com/2023/02/httpswodewangzhishime.html . Ref:  https://wodewangzhishime.blogspot.com/2021/12/httpswodewangzhishime_28.html?m=1   . . . Me: The above picture is a transistor-latch . . This latch is formed by one PNP transistor and one NPN transistor.  When we give a positive voltage to the gate of T1, T1 will be conducted forever.  We call that a latch. Me: How can we let a latch unlatch ?? . VSS stand for source of power. . 1) Give a negative voltage to the gate of T1 2) Cut the power of T2.  3) Let D1 forward bias. . John: A latch is to temporarily latch the data in the memory, when the latch unlatch, the memory will lose forever.

https://wodewangzhishime.blogspot.com/2023/02/translate-selected-text.html . Ref:  https://wodewangzhishime.blogspot.com/2023/02/if-ipaddress133133-nathon-road.html . . . John : The usage of the circuit of Master-Slave is that. . 1) The Clock line is in an up-cycle.  . 2) The master can't be input cause the Clock of the Master is in a Down-cycle. Note: there's an inverter in the master.  . 4) The master can only output.  . 5) The Slave can be input cause the Clock of the slave is in an Up Cycle.  . . John : Now, we mention about fields of datas. Here're 4 fields. They are,  . Subject [Register A] Object [Register B] Interrupt status [SPI] Data bus Width [1 bit] Left_Right_Shift [Right] Acknowledged [Slave] <--- It shows that the connection is good. . . If acknowledge = slave { For (int i = 0; i < 20; i++) { <--- Data bus width [1 bit] Sum = Sum + i; <-- Here mean bit by bit right shift. if (i = 19) { MOV buffer, Sum. <---- Miuson hack this c...

  https://wodewangzhishime.blogspot.com/2023/02/if-ipaddress133133-nathon-road.html Ref:  https://wodewangzhishime.blogspot.com/2022/06/httpswodewangzhishime_8.html . . . . . John: There're 3 pictures above. Me: OK. John: The 1st picture explain to you what is 3 phase. Me: OK. John: Now, look at the 2nd picture. It is about chemistry. It is about delocalization of electrons. Me: OK. John: The current is flowing to the right hand side. Me: OK. John: Both a , b , c are at different phase.  a is at phase 3, b is at phase 2 and c is at phase 1. Me: OK. . John: We look at the 3rd picture. It is about electronic. Me: OK. John: The current is flowing to the right hand side.  a is at phase 3.  b is at phase 2.  c is at phase 1.

https://wodewangzhishime.blogspot.com/2022/10/httpswodewangzhishime.html?m=1 . Ref: https://kamchihau.blogspot.com/2022/08/heat-expand-cold-shrink.html . . . . It is level trigger, not edge trigger. . if (input voltage between 3V and 10V) { output = 1; } else { output = 0; } . Consequently, input = 3V or 4V or 5v or 6v or 7v or 8v or 9v or 10v, output is still 1. . Serial input = edge trigger. . Left or right shift. Parallel input = level trigger. . No left or right shift. . The output is ouput to the output line. .

  https://wodewangzhishime.blogspot.com/2022/07/httpswodewangzhishime.htm .  Ref:  https://wodewangzhishime.blogspot.com/2022/03/httpswodewangzhishime_73.html . ... . . . . . . John: Look at the 1st picture.  Originally, the master of SPI use the clock line of the system. At the same time, the master of SPI use the line of parallel in-out of the system. However, hacker the system.  Finally, it become, . Subject [master of spi] Interrupt [the clock line of RJ45] <---- Originally, it is clock line of system. Parallel input output line [Parallel input output lines from RJ45] <--- Originally, it is the parallel input output line from the system. Object [slave of spi] Value [pending]. . Me: After hacking, the "master of SPI" share the data line and the clock line with RJ45. . John: The master of SPI not only "share" the data line and clock line with RJ45 , but also the master of Spi share the modulator of RJ45 . . Me: OK. . John: Look at the 3rd picture. C...

  https://wodewangzhishime.blogspot.com/2022/07/cai-yourong-spy.html . Ref:  https://wodewangzhishime.blogspot.com/2021/07/httpswodewangzhishime_10.html?m=1 . .. . . . John: There're 2 pictures above. Which one is correct. . Me: The 2nd picture is correct. . John: You're wrong. The 1st picture is correct. . Me: Why? . John: There's a circuit in the 1st picture.  This circuit is called Circuit A. In circuit A, the frequency is strange and unbalance. The left-side branch is 90Mhz. However, the right-side branch is 100Mhz. . John: Because, the right-side branch is 100Mhz. As a result, a electrical current of 100Mhz is induced in Circuit B. And then, it is horrible. Me: Why? John: Read the followings. . 1) The resonance frequency of circuit A is 80Mhz. (fc = 80) <---- fc stand for central frequency. . 2) The resonance frequency of cirucit B is 100Mhz. (fc + deviation = 100) . John: If an electrical current of 100 Mhz is induced in Circuit B,  indeed, between the induc...

  https://wodewangzhishime.blogspot.com/2022/06/what-does-he-need.html . Ref:  https://wodewangzhishime.blogspot.com/2022/06/httpswodewangzhishime_70.html   . . John: There're plenty protocol of communications. You might have a look . //.  https://instrumentationblog.com/communication-protocols/ .   For example, RJ45, I2C, USB, SPI, and, so on and on.  Now, we use I2C as an example. Me: OK. John: At the picture above, do you see that there're 2 chips? They are Chip A and Chip B.  They use the interface of I2C to connect to each others.  Chip A is master. Chip B is slave. That mean Chip B must use the clock line of Chip A. Me: OK. . Inside Chip A, there're 2 clock line. 1) The clock line of RJ45 2) The clock line of system. . John: Then, which clock line does (the register of I2C of the master) choose? Me: Normally, (the register of I2C of the master) use the clock line of System. John: However, hackers hack it. It become . Subject [the regis...