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  https://wodewangzhishime.blogspot.com/2024/02/blog-post.html . Ref:  https://wodewangzhishime.blogspot.com/2024/02/blog-post.html  . . . .  John : See the 1st picture.  It's an extreme condition.  RJ45 is indeed at down cycle.  Therefore,  the clock line of R0 is at down cycle.  However,  the parallel output line of R0 is at up cycle.  Me: RJ45's Circuit is hacked by hacker.  Me: R0 can't output its value onto the parallel output line.  John : Correct. See the 2nd picture.  It's another extreme example. Rj45 provide power supply to the modulator.  In fact,  the modulator is at the Up Cycle.  The clock line of R0 is at the Up Cycle too.  However,  the parallel input line of R0 is at the down system.  . Me: R0 can't be input.  . John : It's true. 

  https://wodewangzhishime.blogspot.com/2023/12/blog-post_14.html   . Ref:  https://wodewangzhishime.blogspot.com/2023/12/blog-post_14.html . . . Me: There're 4 pictures above. . We mention the 1st picture. There is a full wave rectifier. . .When the smoothing capacitor discharge, the gap between the Up and Down cycle is filled. . Consequently, the wave-form of the direct current become smooth. . John: OK. . Me: Now, we look at the 2nd picture. . Case 1. high frequency  <--- The curve is very smooth. . The discharge of the smoothing capacitor can easily fill the gap. . Case 2. middle frequency <--- The curve isn't smooth. . The discharge of the smoothing capacitor can hardly fill the gap. . Case 3. low frequency <--- The curve can't continue. . . The direct current is broken. . The discharge of the smoothing capacitor can't fill the gap. . John: Now, we look at the 2nd picture. . . 1) In direct current, if the frequency is high, the discharge of the smoothi...

  https://wodewangzhishime.blogspot.com/2023/12/blog-post_43.html . Ref:  https://wodewangzhishime.blogspot.com/2023/12/blog-post_43.html  . . . . John: There're 2 pictures above.  The 1st one is the original one.  R0 send out a signal of (0111). Me: Ok. John : Now, we see the 2nd picture.  . Me: Ok.  . John: Because the parallel output line of R0 is a branch of RJ45's Clock line, hacker hack the RJ45's Clock line and change the signal to (1000). .

https://wodewangzhishime.blogspot.com/2023/12/blog-post_13.html . Ref:  https://wodewangzhishime.blogspot.com/2023/12/blog-post_13.html  . . . John : See the Picture above.  There's a frequency mixer which mix the signal from the output of R0 and the signal from the Clock line of RJ45.  Me: R0 output.  Therefore,  RJ45 Clock line must be in down cycle.  . 1) The Signal from the Clock line of RJ45 must be wave inside which there is no carrier wave.  . 2) The carrier wave should be the output from R0. . 3) And then,  the signal from both R0 and RJ45 mix together at the frequency mixer.

  https://wodewangzhishime.blogspot.com/2023/12/blog-post_12.html . Ref:  https://wodewangzhishime.blogspot.com/2023/12/blog-post_12.html . . . Me: The upper picture use the inverters to delay the circuit. . However, the lower picture use the JK-Flip Flop to delay the circuit.

https://wodewangzhishime.blogspot.com/2023/12/sequential-99.html . . Ref:  https://wodewangzhishime.blogspot.com/2023/12/sequential-99.html . . .   . . Me: This article ( https://wodewangzhishime.blogspot.com/2023/12/blog-post_11.html ) mention that if I input 3-2-1-4, it stack overflow. Becuase 3-2 are too close to each other. .  . John: It is the problem of frequency. Me: Yes, . . Look at the 1st picture of this article. . It is an RJ45 circuit. .  This circuit use a capacitor and an inductor to form a filter. John: What's the filter for?? Me: For filtering signal. . . It let the signal within the boundary of frequency pass through. John: That mean, it let 3-2 enter the ground. Me: Yes,

https://wodewangzhishime.blogspot.com/2023/12/blog-post_11.html . . Ref:  https://wodewangzhishime.blogspot.com/2023/12/blog-post_11.html   . . . . Me: The following 4 articles mention how fields work in RAM. . They are very important. . Why ?? I answer you later. Maybe,you can read them first. 1)  https://wodewangzhishime.blogspot.com/2021/11/httpswodewangzhishime_96.html 2)  https://kamchihau.blogspot.com/2022/10/httpskamchihau_17.html?m=1 3)  https://wodewangzhishime.blogspot.com/2022/06/satellite-for-loop.html 4)  https://kamchihau.blogspot.com/2022/11/httpskamchihau.html . Me: We deep inside the theme of today. There're 6 fields inside a "register of RAM".  Subject [],  Role [],  interrupt status [],  value's type [],  object [],  Value [].   . I use (((Mov object, value))) as an example.  <--- In C++, it is ((( int object = value ))); . Originally, it is (((Mov register_a, value)))  <--- Note: in C++,...

https://wodewangzhishime.blogspot.com/2023/12/sequential-94-cross.html . Ref:  https://wodewangzhishime.blogspot.com/2023/08/is-that-due-to-wish-to-teach-americas.html . . . Me: https://wodewangzhishime.blogspot.com/2023/12/sequential-94-cross.html  . .This article mention that if you put too many inverters, the circuit delay too much. . Consequently, stack overflow occur. . Today, we give one more example in which the cirucit doesn't put too many inverters, however, stack overflow sitll occur. . I'm gonna input 3-2-1-4.   3-2 comply with the combination of NPN-PNP. . Look at the above picture. . There're 2 inverters only. . However, 3-2 both comply with the combination of NPN-PNP. . Consequently, stack overflow occur. . John: Because, 3-2 are closed to each other. . The frequency is too high. Me: In this case, stack overflow occur. . .

  https://wodewangzhishime.blogspot.com/2023/12/blog-post_2.html . Ref:  https://wodewangzhishime.blogspot.com/2023/12/blog-post_2.html  .  . . Me: You may consult it . . https://wodewangzhishime.blogspot.com/2023/12/blog-post_2.html .  Inverter is to delay the current flow.  Normally, we put a pair of inverter. . In a single Up cylce, I input 3-2-1-4, indeed, only "3" can be accepted. Why ?? Because, only "3" comply with the combination of NPN-PNP. . If you put too many inverters, the consequency is that not only "3" comply with the combination of NPN-PNP, but, "2" also comply with the combination of NPN-PNP. . Consequently, stack overflow occur.

https://wodewangzhishime.blogspot.com/2023/12/sequential-92-smoothing-capacitor.html . Ref:  https://wodewangzhishime.blogspot.com/2023/12/sequential-92-smoothing-capacitor.html   . . . . . 1) About stack overflow, 2) Look at the 1st and 2nd pictures. . Note: The inverter delay the fow of current. The speed of the flow of current of line one is slower than the speed of the flow of current of line two. . 3) When the combination is npn-pnp, the up cycle is at the falling edge.  . 4) Look at the 3rd picture.  . John: When you input 3-2-1-4 to the gate of R1 during one up cycle, indeed, only 3 has the combination of NPN and PNP. .   And then , 2-1-4 are discarded. 3. npn pnp 2.  npn npn (discarded) 1.  npn npn (discarded) 4.  pnp npn (discarded) . John: Look at the last picture. . It is a RJ45 circuit. . .During an Up cycle, there're 3-2-1-4. . Me: Indeed, Port A only input with 3. . .And then, 2-1-4 are discarded. . Why ?? . John: Because, only ...

  https://wodewangzhishime.blogspot.com/2023/12/blog-post.html . Ref:  https://wodewangzhishime.blogspot.com/2023/12/blog-post.html   . . John: Before we start, you may read this article first. <  https://kamchihau.blogspot.com/2024/07/sequential-109.html >. Me: OK. . John: This article  < https://wodewangzhishime.blogspot.com/2023/12/blog-post.html >  mention about a stable flip flop. You may read it first.   Me: OK. . John: Now, we start this article. Me: OK. John: At the above picture. There is an Up cycle on the clock line. This up cycle cover R0(0), R0(1), R0(2), R0(3). However, . R0(0)-> stable. R0(1)-> Unstable. R0(2)-> stable. R0(3)-> stable. . John: When R0(1) is unstable, R0(1) become a gap. Me: Then, what does gap mean? John: You may read this article. < https://wodewangzhishime.blogspot.com/2022/04/httpswodewangzhishime_23.html >. It is the meaning of "Gap".

  https://wodewangzhishime.blogspot.com/2023/12/sequential-90-enabling-line.html . Ref:  https://wodewangzhishime.blogspot.com/2023/12/sequential-90-enabling-line.html . . . John: The above picture is a circuit of flip flop. I guess you know that . . When set and reset is 1-0 -> 1 0-1 -> 0 0-0 -> remain the same.  1-1 -> toggle or illegal.  . John: Do you see an Up cycle on the clock line? Me: Yes,. John: This Up cycle is stable.

  https://wodewangzhishime.blogspot.com/2023/11/httpswodewangzhishime_29.html . Ref: https://wodewangzhishime.blogspot.com/2023/11/httpswodewangzhishime_29.html . . . John : This article is about the "width" of data bus, e.g., 4 bits, 8 bits, 32 bits.  https://wodewangzhishime.blogspot.com/2022/04/httpswodewangzhishime_23.html?m=1 . You might have a look first.  Me: Ok. . John : See the above 2nd Picture. All control bus, data bus and address bus are the branch of Clock line of RJ45. . Me: In another words,  if hacker hack the Clock line of RJ45,  hacker can hack the system bus (Control, address and data bus). . John : Yes, take a look.  . 1) Address bus. . 2) Data bus, e.g., parallel input output line, serial input line.  . __ . 3) Control bus,  e.g.,  interrupt status [ RJ45 clock line], Falling edge trigger[ true ],   Left_Right_Shift status [ Right shift ], Load_Shift_status [  shifting ] .   Acknowledge [Slave] Bus w...

https://wodewangzhishime.blogspot.com/2023/11/httpswodewangzhishime.html . Ref: https://wodewangzhishime.blogspot.com/2023/11/httpswodewangzhishime.html . . . . . Me: I mention stack overflow in this article. . You can have a look at this article first. https://wodewangzhishime.blogspot.com/2023/11/httpswodewangzhishime.html . . Look at the first picture. If you input 3-1-4-2-4-1-3, the output is 3-3-3-3-3-3-3-3. You must 3-(input down cycle)1-(input down cycle)4-(input down cycle)2-(input down cycle)4-(input down cycle)1-(input down cycle)3 . Or. . You can 3-(power source, down cycle)1-(power source ,down cycle)4-(power source ,down cycle)2-(power source ,down cycle)4-(power source ,down cycle)1-(power source ,down cycle)3

https://wodewangzhishime.blogspot.com/2023/11/ref-httpswodewangzhishime.html . Ref: https://wodewangzhishime.blogspot.com/2023/11/ref-httpswodewangzhishime.html .  . . Those pictures are the difference between a latch and a modulator. . 1) The first picture is a latch. . During an Up cycle, I input 3-1-4-2-4-1-3. . The output remain 3-3-3-3-3-3-3. . Why ?? Because, it is a latch. . The output depends on the feedback. . If I wanna a 3-1-4-2-4-1-3, what should I do?? You should 3-(down cycle)1-(down cycle)4-(down cycle)2-(down cycle)4-(down cycle)1-(down cycle)3 . 2) The second picture is a modulator. . If I input 3-1-4-2-4-1-3, the output is 3-1-4-2-4-1-3. . Why ?? Because, the output is independent from the feeback. . 3) The third pictue is clear. . . . If there is a feedback, it is a latch. . If there is no feedback, it is a modulator.

https://wodewangzhishime.blogspot.com/2023/08/2001-4-airplanes-were-hacked.html?m=1 . Ref: https://wodewangzhishime.blogspot.com/2021/09/httpswodewangzhishime_11.html . . . . . . . John: Look at the first picture. Ther're 2 way of connection of RJ45. Both ways are OK. Let me explain the 2nd picture. Me: OK. John: When Port A is being input, Port B is with the status of outputing. Me: OK. . John: Look at the 3rd picture. When Port B is being input, Port A is with the status of outputing.

https://wodewangzhishime.blogspot.com/2023/08/is-that-due-to-wish-to-teach-americas.html . Ref:  https://wodewangzhishime.blogspot.com/2021/11/httpswodewangzhishime_83.html . . John: This article ( https://wodewangzhishime.blogspot.com/2022/03/httpswodewangzhishime_7.html ) mention about the direction of current flow of RJ45. Me: OK. John: Now, we look at the 3rd picture. The direction of current flow of the secondary coil must be opposite to the direction of the current flow of the primary coil. Me: Correct. If we don't do that, the current flow of the primary coil will stop. . John: Now, I change the story a little. Me: OK. . John: The direction of the current flow of the secondary is occassionally opposite to the direction of the current flow of the primary coil. Me: Occassionally? John: Yes,. Me: Then, a carrier wave will be formed. John: Now, we look at the 2nd picture. Me: OK. . If the direction of the current flow the Port B is occassionally same as the direction of the curr...

https://wodewangzhishime.blogspot.com/2023/08/blog-post.html . Ref: https://wodewangzhishime.blogspot.com/2021/09/accompany-journalists.html . . . John : Take a look.   https://kamchihau.blogspot.com/2022/09/different-frequency.html?m=1  . It's about a 3rd party's common network.  Now, we talk about network switching.  Me: Ok.  John : SIM Card A and B are in different network.  In order to communicate with each other,  SIM card A switch switch himself and the Cache of his physical address to France's network temporarily.  Me: In this case,  SIM card A is the master and SIM Card B is the slave.  John : Yes,  SIM card A pay the Communication Cost. 

  https://wodewangzhishime.blogspot.com/2023/07/blog-post_31.html . . Ref:  https://kamchihau.blogspot.com/2023/08/blog-post.html   . . . John: Before we start, you may read this article ( https://wodewangzhishime.blogspot.com/2023/08/2001-4-airplanes-were-hacked.html ). . Me: OK. John: If the direction of current flow of port B is "occassionally" same as that of port A, there will be carrier wave formed. . Me: OK. John: Look at the picture above. Those carrier wave will affect the data input of Port A. Me: Those carrier wave also affect the Clock line. Consequently, register R1, 2, 3 become unstable.

  https://wodewangzhishime.blogspot.com/2023/07/me-look-at-this-article.html . Ref: https://wodewangzhishime.blogspot.com/2023/07/me-look-at-this-article.html . . Subject [C3] interrupt [system clock line] Line [the line of parallel in-out of the system] . Note: In regard to the line of parallel in and out, you may have a look at this article ( https://wodewangzhishime.blogspot.com/2022/10/httpswodewangzhishime.html ). Cache Line [L2]. Object [pending]. . John: Take a look at this article  https://wodewangzhishime.blogspot.com/2021/11/httpswodewangzhishime_83.html . At the line of L1, only C2 is available. Why? Me: If too many Cache is being compared and checked at the line of L1, the speed is too low. John: The process is blocked? Me: Correct. John: Therefore, we must divide it into 3 line3. Line of L1, L2, and, L3. Me: Correct. . === . John: Actually, there's another way we can solve the problem of "Blocking". Take a look at the 1st picture above. We have C1, P1, C2,...

  https://wodewangzhishime.blogspot.com/2023/07/blog-post.html . Ref: https://wodewangzhishime.blogspot.com/2023/07/blog-post.html . . . John: The above picture is the process of output of RJ45. The first step is MOV Port C, value. Me: And then? . 1) The data input of R3 is from the data output of R2 (R2 right shift to R3) 2) The data input of R2 is from the data output of R1. (R1 right shift to R2) . John: Then, where is the data input of R1 from? Me: From the clock line. John: That mean, the data-input line of R1 is linked to the clock line. Me: Correct. When the clock line is up cyle, R1 is being triggered. We call that point as "Output triggering point". John: When Port A is triggered, R1 right shift to R2, R2 right shift to R3, etc. Me: Finally, R3 output. .

  https://wodewangzhishime.blogspot.com/2023/02/httpswodewangzhishime.html . Ref: https://wodewangzhishime.blogspot.com/2021/12/httpswodewangzhishime_28.html?m=1   . . . Me: The above picture is a transistor-latch . . This latch is formed by one PNP transistor and one NPN transistor. . T1,2 stand for transistor 1, 2. John: When we give a positive voltage to the gate of T1, T1 will be conducted forever. . We call that a latch. . Me: How can we let a latch unlatch ?? . VSS stand for source of power. . 1) Give a negative voltage to the gate of T1 or 2) Cut the VCC. . That mean , cut the source of power. . John: A latch is to temporarily latch the data in the memory, when the latch unlatch, the memory will lose forever.

https://wodewangzhishime.blogspot.com/2023/02/translate-selected-text.html . Ref:  https://wodewangzhishime.blogspot.com/2023/02/if-ipaddress133133-nathon-road.html . . . John : The usage of the circuit of Master-Slave is that. . 1) The Clock line is in an up-cycle.  . 2) The master can't be input cause the Clock of the Master is in a Down-cycle. Note: there's an inverter in the master.  . 4) The master can only output.  . 5) The Slave can be input cause the Clock of the slave is in an Up Cycle.  . . John : Now, we mention about fields of datas. Here're 4 fields. They are,  . Subject [Register A] Object [Register B] Interrupt status [SPI] Data bus Width [1 bit] Left_Right_Shift [Right] Acknowledged [Slave] <--- It shows that the connection is good. . . If acknowledge = slave { For (int i = 0; i < 20; i++) { <--- Data bus width [1 bit] Sum = Sum + i; <-- Here mean bit by bit right shift. if (i = 19) { MOV buffer, Sum. <---- Miuson hack this c...

  https://wodewangzhishime.blogspot.com/2023/02/if-ipaddress133133-nathon-road.html Ref:  https://wodewangzhishime.blogspot.com/2022/06/httpswodewangzhishime_8.html . . . . . John: There're 3 pictures above. Me: OK. John: The 1st picture explain to you what is 3 phase. Me: OK. John: Now, look at the 2nd picture. It is about chemistry. It is about delocalization of electrons. Me: OK. John: The current is flowing to the right hand side. Me: OK. John: Both a , b , c are at different phase.  a is at phase 3, b is at phase 2 and c is at phase 1. Me: OK. . John: We look at the 3rd picture. It is about electronic. Me: OK. John: The current is flowing to the right hand side.  a is at phase 3.  b is at phase 2.  c is at phase 1.