sequential (93) delay circuit

https://wodewangzhishime.blogspot.com/2023/12/sequential-92-smoothing-capacitor.html

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Ref: https://wodewangzhishime.blogspot.com/2023/12/sequential-92-smoothing-capacitor.html 

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1) About stack overflow,

2) Look at the 1st and 2nd pictures.

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Note: The inverter delay the fow of current.

The speed of the flow of current of line one is slower than the speed of the flow of current of line two.

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3) When the combination is npn-pnp, the up cycle is at the falling edge. 

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4) Look at the 3rd picture. 

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John: When you input 3-2-1-4 to the gate of R1 during one up cycle, indeed, only 3 has the combination of NPN and PNP. .   And then, 2-1-4 are discarded.

3. npn pnp

2. npn npn (discarded)

1. npn npn (discarded)

4. pnp npn (discarded)

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John: Look at the last picture. . It is a RJ45 circuit. . .During an Up cycle, there're 3-2-1-4.

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Me: Indeed, Port A only input with 3. . .And then, 2-1-4 are discarded. . Why ??

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John: Because, only "3" comply with the combination of NPN-PNP.