sequential (93) delay circuit

https://wodewangzhishime.blogspot.com/2023/12/blog-post.html?m=1

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Ref: https://chihaukam.blogspot.com/2024/10/take-look-at-it_30.html?m=1

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John:  See the 1st and 2nd pictures. The inverter delay the fow of current. The speed of the flow of current of line one is slower than the speed of the flow of current of line two. When the combination is npn-pnp, the up cycle is at the falling edge. 

Me: Ok.

John: When 3-2-1-4 are input, indeed, only 3 has the combination of NPN and PNP. And then, 2-1-4 are discarded.

3. npn pnp

2. npn npn (discarded)

1. npn npn (discarded)

4. pnp npn (discarded)

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