sequential (33) CPU and RAM (master and slave)

 https://wodewangzhishime.blogspot.com/2022/07/httpswodewangzhishime.htm

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Ref: https://wodewangzhishime.blogspot.com/2022/03/httpswodewangzhishime_73.html .

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John: Look at the 1st picture.

Me: OK.

John: Originally, the circuit of the master of SPI use the clock line of the system. At the same time, the circuit of the master of SPI use the line of parallel in-out of the system. However, hacker hack it.

Me: How to hack it?

John: You may have a look. https://wodewangzhishime.blogspot.com/2023/12/sequential-99.html .

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Hacker hack the circuit of Master of SPI. Finally, it become,

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Subject [circuit of master of spi]

Interrupt [clock line of RJ45] <---- Originally, it is clock line of system.

Data bus [line of parallel in out of RJ45] <--- Originally, it is line of parallel in-out of system.

Object [circuit of slave of spi]

Value [pending].

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Me: After the hacking, the circuit of the master of SPI share the line of parallel in out and the clock line with the circuit of RJ45.

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John: The circuit of the master of SPI not just "share" the line of parallel in out and clock line with the circuit of RJ45, but also the modulator of the circuit of RJ45 .

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Me: OK.

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John: Look at the 3rd picture. Chip B is the slave. The slave use the clock line of the master. If the master use the clock line of the circuit of RJ45, the slave use the clock line of the circuit of RJ45.

Me: Correct.