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  https://wodewangzhishime.blogspot.com/2023/12/blog-post_43.html . Ref:  https://wodewangzhishime.blogspot.com/2023/12/blog-post_43.html  . . . John: This article ( https://wodewangzhishime.blogspot.com/2024/02/httpswodewangzhishime.html ) say that parallel in out line is a branch of the Clock line of RJ 45. Me: OK. John: Look at the picture above. Do you see a frequency mixer? This mixer mix the frequency of the output of the modulator and the clock line of RJ45. Me: OK. John: Originally, the modulator output 3-2-1-4, and then, input them to a - b - c - d. Because, the parallel in out line is the branch of the clock line of RJ45. If the clock line of RJ 45 is hacked by hackers. Hackers can change 3-2-1-4 into 0-4-0-4. Consequently, the input to a - b - c - d is 0 , 4, 0, 4. . Me: Take a look at this article . ( https://kamchihau.blogspot.com/2024/07/sequential-109.html ) .

https://wodewangzhishime.blogspot.com/2023/12/blog-post_13.html . Ref:  https://wodewangzhishime.blogspot.com/2023/12/blog-post_13.html  . . . . John: This article ( https://wodewangzhishime.blogspot.com/2023/12/sequential-99.html ) say that Left shift is a way of hacking. Me: To some extent "Yes". John: OK. In reality, we don't need "Left-Shift" to change the contents of (subject-interrupt-object). Me: Then, what do we need? John: We need to hack the clock line of RJ45. Read this article. (  https://wodewangzhishime.blogspot.com/2023/12/blog-post_14.html ). This article say "parallel in out line" is the branch of the clock line of RJ45. Me: OK. John: Look at the picture above. Originally, the output of the field of subject-interrupt-object is 0-1-0. . Because, the parallel out line is a branch of the clock line of RJ45, hacker hack the clock line of RJ45 and then hacker can control the parallel out line. Hacker let the output of subject-interrupt-obj...

  https://wodewangzhishime.blogspot.com/2023/12/blog-post_12.html . Ref:  https://wodewangzhishime.blogspot.com/2023/12/blog-post_12.html . . . Me: The upper picture use the inverters to delay the circuit. . However, the lower picture use the JK-Flip Flop to delay the circuit.

https://wodewangzhishime.blogspot.com/2023/12/sequential-99.html . . Ref:  https://wodewangzhishime.blogspot.com/2023/12/sequential-99.html . . .   . . Me: This article ( https://wodewangzhishime.blogspot.com/2023/12/blog-post_11.html ) mention that if I input 3-2-1-4, it stack overflow. Becuase 3-2 are too close to each other. .  . John: It is the problem of frequency. Me: Yes, . . Look at the 1st picture of this article. . It is an RJ45 circuit. .  This circuit use a capacitor and an inductor to form a filter. John: What's the filter for?? Me: For filtering signal. . . It let the signal within the boundary of frequency pass through. John: That mean, it let 3-2 enter the ground. Me: Yes,

https://wodewangzhishime.blogspot.com/2023/12/blog-post_11.html . . Ref:  https://wodewangzhishime.blogspot.com/2023/12/blog-post_11.html   . . . . Me: The following 4 articles mention how fields work in RAM. . They are very important. . Why ?? I answer you later. Maybe,you can read them first. 1)  https://wodewangzhishime.blogspot.com/2021/11/httpswodewangzhishime_96.html 2)  https://kamchihau.blogspot.com/2022/10/httpskamchihau_17.html?m=1 3)  https://wodewangzhishime.blogspot.com/2022/06/satellite-for-loop.html 4)  https://kamchihau.blogspot.com/2022/11/httpskamchihau.html . Me: We deep inside the theme of today. There're 6 fields inside a "register of RAM".  Subject [],  Role [],  interrupt status [],  value's type [],  object [],  Value [].   . I use (((Mov object, value))) as an example.  <--- In C++, it is ((( int object = value ))); . Originally, it is (((Mov register_a, value)))  <--- Note: in C++,...

https://wodewangzhishime.blogspot.com/2023/12/sequential-94-cross.html . Ref:  https://wodewangzhishime.blogspot.com/2023/08/is-that-due-to-wish-to-teach-americas.html . . . Me: https://wodewangzhishime.blogspot.com/2023/12/sequential-94-cross.html  . .This article mention that if you put too many inverters, the circuit delay too much. . Consequently, stack overflow occur. . Today, we give one more example in which the cirucit doesn't put too many inverters, however, stack overflow sitll occur. . I'm gonna input 3-2-1-4.   3-2 comply with the combination of NPN-PNP. . Look at the above picture. . There're 2 inverters only. . However, 3-2 both comply with the combination of NPN-PNP. . Consequently, stack overflow occur. . John: Because, 3-2 are closed to each other. . The frequency is too high. Me: In this case, stack overflow occur. . .

  https://wodewangzhishime.blogspot.com/2023/12/blog-post_2.html . Ref:  https://wodewangzhishime.blogspot.com/2023/12/blog-post_2.html  .  . . Me: You may consult it . . https://wodewangzhishime.blogspot.com/2023/12/blog-post_2.html .  Inverter is to delay the current flow.  Normally, we put a pair of inverter. . In a single Up cylce, I input 3-2-1-4, indeed, only "3" can be accepted. Why ?? Because, only "3" comply with the combination of NPN-PNP. . If you put too many inverters, the consequency is that not only "3" comply with the combination of NPN-PNP, but, "2" also comply with the combination of NPN-PNP. . Consequently, stack overflow occur.

https://wodewangzhishime.blogspot.com/2023/12/sequential-92-smoothing-capacitor.html . Ref:  https://wodewangzhishime.blogspot.com/2023/12/sequential-92-smoothing-capacitor.html   . . . . . 1) About stack overflow, 2) Look at the 1st and 2nd pictures. . Note: The inverter delay the fow of current. The speed of the flow of current of line one is slower than the speed of the flow of current of line two. . 3) When the combination is npn-pnp, the up cycle is at the falling edge.  . 4) Look at the 3rd picture.  . John: When you input 3-2-1-4 to the gate of R1 during one up cycle, indeed, only 3 has the combination of NPN and PNP. .   And then , 2-1-4 are discarded. 3. npn pnp 2.  npn npn (discarded) 1.  npn npn (discarded) 4.  pnp npn (discarded) . John: Look at the last picture. . It is a RJ45 circuit. . .During an Up cycle, there're 3-2-1-4. . Me: Indeed, Port A only input with 3. . .And then, 2-1-4 are discarded. . Why ?? . John: Because, only ...

  https://wodewangzhishime.blogspot.com/2023/12/blog-post.html . Ref:  https://wodewangzhishime.blogspot.com/2023/12/blog-post.html   . . John: Before we start, you may read this article first. <  https://kamchihau.blogspot.com/2024/07/sequential-109.html >. Me: OK. . John: This article  < https://wodewangzhishime.blogspot.com/2023/12/blog-post.html >  mention about a stable flip flop. You may read it first.   Me: OK. . John: Now, we start this article. Me: OK. John: At the above picture. There is an Up cycle on the clock line. This up cycle cover R0(0), R0(1), R0(2), R0(3). However, . R0(0)-> stable. R0(1)-> Unstable. R0(2)-> stable. R0(3)-> stable. . John: When R0(1) is unstable, R0(1) become a gap. Me: Then, what does gap mean? John: You may read this article. < https://wodewangzhishime.blogspot.com/2022/04/httpswodewangzhishime_23.html >. It is the meaning of "Gap".

  https://wodewangzhishime.blogspot.com/2023/12/sequential-90-enabling-line.html . Ref:  https://wodewangzhishime.blogspot.com/2023/12/sequential-90-enabling-line.html . . . John: The above picture is a circuit of flip flop. I guess you know that . . When set and reset is 1-0 -> 1 0-1 -> 0 0-0 -> remain the same.  1-1 -> toggle or illegal.  . John: Do you see an Up cycle on the clock line? Me: Yes,. John: This Up cycle is stable.

  https://wodewangzhishime.blogspot.com/2023/11/httpswodewangzhishime_29.html . Ref: https://wodewangzhishime.blogspot.com/2023/11/httpswodewangzhishime_29.html . . . John : This article is about the "width" of data bus, e.g., 4 bits, 8 bits, 32 bits.  https://wodewangzhishime.blogspot.com/2022/04/httpswodewangzhishime_23.html?m=1 . You might have a look first.  Me: Ok. . John : See the above 2nd Picture. All control bus, data bus and address bus are the branch of Clock line of RJ45. . Me: In another words,  if hacker hack the Clock line of RJ45,  hacker can hack the system bus (Control, address and data bus). . John : Yes, take a look.  . 1) Address bus. . 2) Data bus, e.g., parallel input output line, serial input line.  . __ . 3) Control bus,  e.g.,  interrupt status [ RJ45 clock line], Subject [ Register A ],   Left_Right_Shift status [ Right shift ], Load_Shift_status [  shifting ].   Acknowledge [Slave] Bus width [1...