sequential (72) Frequently used cache (2)

 https://wodewangzhishime.blogspot.com/2023/07/me-look-at-this-article.html

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Ref:https://wodewangzhishime.blogspot.com/2023/07/me-look-at-this-article.html

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Subject [C3]
interrupt [system clock line]
Data bus [the line of parallel in-out of the system] . Note: In regard to the line of parallel in and out, you may have a look at this article (https://wodewangzhishime.blogspot.com/2022/10/httpswodewangzhishime.html).
Cache Line [L2].

Object [pending].

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John: Take a look at this article https://wodewangzhishime.blogspot.com/2021/11/httpswodewangzhishime_83.html . At the line of L1, only C2 is available. Why?

Me: If too many Cache is being compared and checked at the line of L1, the speed is too low.

John: The process is blocked?

Me: Correct.

John: Therefore, we must divide it into 3 line3. Line of L1, L2, and, L3.

Me: Correct.

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John: Actually, there's another way we can solve the problem of "Blocking". Take a look at the 1st picture above. We have C1, P1, C2, P2. They represent Cache 1, Parallel-line 1, Cache 2, Parallel-line2. Do you find that C2 put himself on P2 rather than P1?

Me: Yes,.

John: Indeed, C2 didn't block the "comparison and checking" of C1 and C3. Because, C1 and C3 are at the line of P1.

Me: Correct.

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John: The most funny thing is that C4 didn't put himself on P1. Nor did C4 put himself on P2. Indeed, C4 is at the stage of Mask-interrup. In code, we inteprete it in this way.

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Subject [C4]

Interrupt [Mask-interrupt]

Data bus [Pending]. <--- What is data bus ? Have a look . https://wodewangzhishime.blogspot.com/2022/10/httpswodewangzhishime.html .

Cache line [Pending]. <--- C4 isn't at the line of L1. Nor is C4 at the line of L2 or L3.

Object [Pending].