sequential (72) Frequently used cache

 https://wodewangzhishime.blogspot.com/2023/07/me-look-at-this-article.html

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Ref:https://wodewangzhishime.blogspot.com/2023/07/me-look-at-this-article.html

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Register 5 can't send anything to register 4 "directly". . 

Register 5 must send to the cache of R4 first. . 

And then, the cache of R4 will send to the modulator. 

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Lastly, the modulator will send to Register 4.

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John: There're the cache of R1,2,3,4,5. .Next to the cache of R1,2,3,4,5, there 're Xor gates which are used to compare and check. . If the signal from register 5 enter the loop-back line, does the signal of register 5 need to goes into the Xor gate of R1,2,3,4,5 for comparing and checking ??

Me: Indeed, the signal of register 5 need go through the xor gate of R1,2,3,4,5 . However, in reality, it doesn't need it.

John: Why ??

Me: There're 3 Loop-back line. . They are L1 loop-back line, L2 loop-back line, L3 loop-back line. . Indeed, on the L1 loop-back line, only R4 has an Xor gate. . On the L1 loop-back line, R1,2,3,5 don't have an Xor gate. . .That mean, when the signal of register 5 enter the L1 Loop-back line, the signal doesn't need to check R1,2,3,5. . . This signal only need to check R4.

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1) The lesser number of Xor gate is on the L1 loop-back line, 

2) it means that ,

3) the lesser comparison is needed for the signal of R5, 

4) as a result, 

5) the faster the job of the signal of R5  finished.

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The Xor gate of most frequently used Cache is put on L1 Loop-back line.

The Xor gate of middle frequently used Cache is put on L2 Loop-back line.

The Xor gate of less frequently used Cache is put on L3 Loop-back line.

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John: I change the story. . I assume that the signal of Register 5 need to compare with R2. . If the signal of register 5 enter L1 Loop-back line, there is no result.

Me: And then, the signal of register 5 will enter L2.

John: Still, there isn't any result.

Me: Lastly, the signal of register 5 enter L3. . He must have a result. .