sequential (75) - - Frequently used cache (1)

https://wodewangzhishime.blogspot.com/2021/11/httpswodewangzhishime_88.html

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Ref: https://kamchihau.blogspot.com/2022/08/angle-effect-in-optical-fiber.html?m=1

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John: See the 1st picture above. We might see C1,2,3,4. The are Cache 1,2,3,4 respectively. We also see the Xor gate. They're used to compare and check. See the 2nd picture above. They work in this way,.

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During the 1st up cycle of the clock line, the datas enter the line of L1. Only L1 is covered.

During the 2nd up cylcle, the datas enter the line of L1 and L2. L1 and L2 are covered.

During the 3rd up cycle, the datas enter the line of L1 and L2 and L3. L1, L2 and L3 are covered.

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Me: OK.

John: Do you find that at the line of L1, only C2 is available for compare and check?

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Me: Yes, only C2 is available for compare and check at the line of L1.

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John: That mean, during the 1st up cycle,  only C2 is compared and checked.

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Me: Correct. C3 must wait until the 2nd up cylce to be compared and checked. Because, C3 is at the line of L2.

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John: In code, we represent them in this way.

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Subject [C3]

interrupt [real interrupt]

Circuit [System Circuit] 

Cache Line [L2].

Object [pending]

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John : We let the most frequently used Cache be moved to L1. We let the less frequently cache be moved to L3.

Me: Ok.