sequential (75) b - - Frequently used cache (1)

https://wodewangzhishime.blogspot.com/2021/11/httpswodewangzhishime_88.html

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Ref: https://wodewangzhishime.blogspot.com/2023/08/blog-post.html 

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John: Have a look at the picture above. We might see C1,2,3,4. The are Cache 1,2,3,4.

Me: OK.

John: You also see the Xor gate.

Me: Yes,.

John: They're used to compare and check. You may have a look at this article (https://wodewangzhishime.blogspot.com/2023/12/sequential-99.html) .,

Me: OK. 

John: Have a look at the 2nd picture above. They work in this way,.

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During the 1st up cycle of the clock line, the datas enter the line of L1. Only L1 is covered.

During the 2nd up cylcle of the clock line, the datas enter the line of L1 and L2. L1 and L2 are covered.

During the 3rd up cycle, the datas enter the line of L1 and L2 and L3. L1, L2 and L3 are covered.

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Me: OK.

John: Do you find that at the line of L1, only C2 is available for compare and check?

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Me: Yes,.  Only C2 is available for compare and check at the line of L1.

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John: That mean, during the 1st up cycle of the clock line, only C2 is compared and checked.

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Me: Correct. C3 must wait until the 2nd up cylce of the clock line to be compared and checked. Because, C3 is at the line of L2.

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John: Correct. Take a look at this article ( https://wodewangzhishime.blogspot.com/2021/11/httpswodewangzhishime_96.html ). In code, we represent them in this way.

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Subject [C3]

interrupt [system clock line]

Data bus [the line of parallel in-out of the system] <--- In regard to the line of parallel in and out, you may have a look at this article (https://wodewangzhishime.blogspot.com/2022/10/httpswodewangzhishime.html).

Cache Line [L2].

Object [pending]