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  https://wodewangzhishime.blogspot.com/2023/07/me-look-at-this-article.html . Ref: https://wodewangzhishime.blogspot.com/2023/07/me-look-at-this-article.html . . Subject [C3] interrupt [system clock line] Data bus [the line of parallel in-out of the system] . Note: In regard to the line of parallel in and out, you may have a look at this article ( https://wodewangzhishime.blogspot.com/2022/10/httpswodewangzhishime.html ). Cache Line [L2]. Object [pending]. . John: Take a look at this article  https://wodewangzhishime.blogspot.com/2021/11/httpswodewangzhishime_83.html . At the line of L1, only C2 is available. Why? Me: If too many Cache is being compared and checked at the line of L1, the speed is too low. John: The process is blocked? Me: Correct. John: Therefore, we must divide it into 3 line3. Line of L1, L2, and, L3. Me: Correct. . === . John: Actually, there's another way we can solve the problem of "Blocking". Take a look at the 1st picture above. We have C1, P1...

  https://wodewangzhishime.blogspot.com/2023/07/blog-post.html . Ref: https://wodewangzhishime.blogspot.com/2023/07/blog-post.html . . . John: The above picture is the process of output of RJ45. The first step is MOV Port C, value. Me: And then? . 1) The data input of R3 is from the data output of R2 (R2 right shift to R3) 2) The data input of R2 is from the data output of R1. (R1 right shift to R2) . John: Then, where is the data input of R1 from? Me: From the clock line. John: That mean, the data-input line of R1 is linked to the clock line. Me: Correct. When the clock line is up cyle, R1 is being triggered. We call that point as "Output triggering point". John: When Port A is triggered, R1 right shift to R2, R2 right shift to R3, etc. Me: Finally, R3 output. .

  https://wodewangzhishime.blogspot.com/2023/02/httpswodewangzhishime.html . Ref: https://wodewangzhishime.blogspot.com/2021/12/httpswodewangzhishime_28.html?m=1   . . . Me: The above picture is a transistor-latch . . This latch is formed by one PNP transistor and one NPN transistor. . T1,2 stand for transistor 1, 2. John: When we give a positive voltage to the gate of T1, T1 will be conducted forever. . We call that a latch. . Me: How can we let a latch unlatch ?? . VSS stand for source of power. . 1) Give a negative voltage to the gate of T1 or 2) Cut the VCC. . That mean , cut the source of power. . John: A latch is to temporarily latch the data in the memory, when the latch unlatch, the memory will lose forever.