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https://wodewangzhishime.blogspot.com/2023/02/translate-selected-text.html . Ref: https://wodewangzhishime.blogspot.com/2023/02/if-ipaddress133133-nathon-road.html . . . . There're 5 conditions on which left or right shift doesn't work. . 1) The latch is being preset and clear. 2) The latch is feedbacking. 3) The latch is being level-trigger. 4) The flip flops is toggling. 5) The commutator is idle . . No up cycle. . No down cycle. Me: Now, we mention condition_3. . The D of master-regiser is being (level triggered). . Consequently, the master-register didn't left shift, nor did the master right shift. . John: Why ?? . Me: When it is right-shift, falling edge trigger. . When it is left-shift, rising edge trigger. . John: When it is level trigger, which side is the register shift?? . Me: No side . . The master-register just output the value to the output line, and then, the signal enter the cache and modulator. . Finally, the modulator send the signal to the slave register.

  https://wodewangzhishime.blogspot.com/2023/02/if-ipaddress133133-nathon-road.html Ref:  https://wodewangzhishime.blogspot.com/2022/06/httpswodewangzhishime_8.html . . . . Me: This picture is just my design. . In reality, it may not be like this. . If the current of the commuator is flowing to the right, and, the cycle is at up, only the NPN is saturated. . . Me: In this case, the output of Q can't left shift. . John: If output of Q left shift, the commutator must be at the down cycle, and the current must flow to the left hand side, and the PNP must be saturated. . .That mean, the PNP receive a signal of zero.

  https://wodewangzhishime.blogspot.com/2022/12/i-know-everythings.html . Ref:  https://kamchihau.blogspot.com/2022/08/heat-expand-cold-shrink.html . . .  . It is level trigger, not edge trigger. . if (input voltage between 3V and 10V) { output = 1; } else  { output = 0; } . Consequently, input = 3V or 4V or 5v or 6v or 7v or 8v or 9v or 10v, output is still 1. . .