sequential (13) no realistic serial circuit (a counter)

https://wodewangzhishime.blogspot.com/2022/02/httpswodewangzhishime_3.html

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Ref:https://wodewangzhishime.blogspot.com/2022/01/httpswodewangzhishime_90.html

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John: Look at the first picture. Clock line is indeed the center tap.

Me: OK.

John: This clock line is shared by "the register of port A" and the "Counter" as well.

Me: OK.

John: Before we start, you may read this article ( https://wodewangzhishime.blogspot.com/2022/03/httpswodewangzhishime_14.html ). It say that there is no realistic serial circuit in the monde.

Me: OK.

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John: There're 2 pictures above. Now, we look at the 2nd picture above. It is a counter. It say if Q0,Q1,Q2 are high, FF4 toggle. However, FF4 will never toggle.

Me: Why will FF4 never toggle?

John: The clock-input for FF3 is forever "Down cycle", Q2 is forever low. How can FF4 toogle? 

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1) Normally, when the clock line is Up cycle indeed, the clock-input for FF3 is Up cycle. 

2) However, in our case, the clock line is Up cycle indeed.  The clock-input For FF3 keep down cycle. 

3) Why does it happen ?  You may have a look at this article (https://wodewangzhishime.blogspot.com/2022/03/httpswodewangzhishime_14.html). 

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