Posts

Showing posts from April, 2022

sequential (63) - System bus

Image
https://wodewangzhishime.blogspot.com/2022/03/httpswodewangzhishime_73.html . Ref:   https://kamchihau.blogspot.com/2022/11/httpskamchihau.html . . John : This article is about System bus.   https://wodewangzhishime.blogspot.com/2023/12/sequential-90-enabling-line.html?m=1  . You may have a look at it first.  Me: Ok. . See the picture above.  1) It is a register of serial input.  2) The field of  value of it has 4 bits. 3) The bit of the left-most is the bit of being input. 4) And, ((S.I. Line)) stand for serial input line. 5) This register right shift.  . Me: Ok.  . John: There're 3 type of data bus of a serial input in term of their width.  . 1) Bus width 4 bits. 2) Bus width 8 bits. 3) Bus width 32 bits. . John : In the picture,  its Bus width us 4 bits. That mean, during 1 up-cycle of the clock line,  maximum 4 bits are allowed to be input together in the field of value of a register of serial input.  This 4 ...